Embodiments of the present disclosure relate to semiconductor devices and, more particularly, to system-on-chip devices that utilize a virtual memory configuration, and further relate to an address translation method thereof.
Mobile devices such as smartphones, tablet personal computers (PCs), digital cameras, MPEG-3 (MP3) players, and personal digital assistants (PDAs) continue to enjoy widespread use. “Application processors”, as they are referred to, have been employed as the driving processor for such mobile devices. Virtual memory management configurations have been employed for improving memory use efficiency in application processors, which commonly include modules or circuit functions referred to as intellectual properties (IPs). In a virtual memory management scheme, IPs access a memory device using a virtual address.
A memory management unit (hereinafter referred to as “MMU”) is hardware responsible for translating a virtual address (hereinafter referred to as “VA”) to a physical address (hereinafter referred to as “PA”) of a memory device. The MMU fetches address translation information, for example page descriptor information, from the memory to translate an input VA to a PA. In addition, the MMU may translate the VA to the PA with reference to a page descriptor to access a memory device.
If a page descriptor corresponding to an access-requested virtual address is already present in an MMU when address translation is performed, additional memory access is not required. Thus, an address translation operation may be promptly carried out. However, in a case where the page descriptor corresponding to the access-requested virtual address is not present in the MMU, an access operation of the memory device is required to occur twice. Accordingly, an address translation overhead is incurred. Since such latency operates as a decisive factor for overall system performance, minimization of address translation overhead is desired.